The field of invention relates to electrical circuitry in general; and, more specifically, to an apparatus and method for a power efficient line driver.
FIG. 1a shows a driver 103 that is responsible for driving information, over communication line 105, to receiver 104. Communication line 105 (which may also be referred to as line 105 for simplicity) is a conductive strip that propagates the information being sent by driver 103 to receiver 104. Depending on the implementation, communication line 105 may correspond to the wiring that exists between a pair of semiconductor chips (e.g., circuitry 101 corresponds to a first semiconductor chip and circuitry 102 corresponds to a second semiconductor chip) or between different regions of the same semiconductor chip (e.g., circuitry 101 corresponds to a first region and circuitry 102 corresponds to a second region where regions 101 and 102 are on the same semiconductor chip).
As semiconductor manufacturing techniques continue to advance, the speed of operation of semiconductor chips continues to increase. As such, the frequencies involved with the driver""s 103 signaling of information to receiver 104 are continue to rise as circuitry 101, circuitry 102 and line 105 are implemented with more sophisticated semiconductor manufacturing technology. Complications arise as signaling frequencies increase, however.
Specifically, as signaling frequency increases, the likelihood increases that imperfections in the shape of the signaling waveform driven onto line 105 by driver 103 (e.g., as caused by back and forth xe2x80x9creflectionsxe2x80x9d of the waveform between the receiver 104 and driver 103) will disturb the reliable reception of data at the receiver 104. An exemplary ideal signaling waveform 112 (i.e., without imperfections) that shows the transition from a logical low to a logical high between times T1 and T2 is shown in FIG. 1b. 
Part of the design challenge in designing circuitry 101, circuitry 102 and line 105, therefore, is reducing the aforementioned likelihood. One technique is to xe2x80x9cterminatexe2x80x9d line 105 with a termination load 106. Termination load 106 is typically designed to have a resistance R that is proximate to the characteristic impedance of line 105. As R approaches the characteristic impedance of line 105, the strength of the reflections between receiver 104 and driver 103 are reduced which, in turn, corresponds to less disturbance in the shape of the signaling waveform 112.
A problem with traditional resistive termination load techniques (such as that described above), however, is the power dissipation that results. Specifically, when a current flows through a resistor, power is dissipated by the resistor according to the relationship P=I2R=V2/R (where I is the current that flows through the resistor, R is the resistance of the resistor, and V is the voltage across the resistor).
Thus, referring to the exemplary waveform 112 of FIG. 1b, power is dissipated by termination load 106 according to: 1) (VOHxe2x88x92Vterm)2/R while a logical high (having a voltage of VOH) is being driven by driver 103 onto line 105; and 2) (Vtermxe2x88x92VOL)2/R while a logical low (having a voltage VOL) is being driven by driver 103 onto line 105. For applications having a large number of high speed signals, the addition of a termination resistance to each high speed line may dramatically increase power consumption resulting in lower reliability and/or decreased battery life (e.g., for handheld applications).